1. Field of Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, in particular, to an FinFET formed on a semiconductor-on-insulator (SOI) substrate and used as a non-volatile memory cell (NVM).
2. Description of Prior Art
One important trend in the integrated circuits is scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) so as to achieve a high integration degree of devices and reduce a cost of manufacture. However, it is well known that a short channel effect occurs with a reduced size of the MOSFET. When the size of the MOSFET is scaled down, a gate of the MOSFET has a smaller effective length and actually controls fewer charges in a depletion region when a gate voltage is applied. Consequently, the MOSFET has a reduced threshold voltage with a reduced channel length.
A conventional planar MOSFET has a tri-layer structure including a gate electrode, a semiconductor layer, and a gate dielectric sandwiched therebetween. A channel region is provided in the semiconductor layer below the gate electrode, and source/drain regions are provided in the semiconductor layer adjacent to and at two opposing sides of the channel region. A silicide layer may be provided on the source/drain regions and then coupled with source/drain electrodes through vias so as to reduce a parasitic resistance or a parasitic capacitance of the device. The planar MOSFET suffers from the short channel effect and has a threshold voltage fluctuating with variation of the channel length.
To suppress the short channel effect, in U.S. Pat. No. 6,413,802 Chenming Hu et al. disclose an FinFET formed on an SOI substrate, comprising a channel region provided in a central portion of a semiconductor fin, and source/drain regions provided at two ends of the semiconductor fin. A gate electrode is provided at both sides of the channel region and surrounds the latter to provide for example a double gate FinFET. Inversion channels are induced at both sides of the fin. The channel region in the fin has a small thickness so that the whole channel region is controlled by the gate, as a result of which, the short channel effect is suppressed.
However, in a conventional FinFET, a gate is provided between and extends parallel to source/drain regions. Since the distance between the source/drain region and the gate is typically so small that capacitive coupling is introduced therebetween, the resultant device has a large parasitic capacitance.
Moreover, the capacitive coupling between the source/drain region and the gate limits the freedom of device design. For example, if one attempts to reduce a parasitic resistance, a thickness of the source/drain region may have to be increased. However, the source/drain region having a larger thickness also means an increased coupling area between the source/drain region and the gate, which in turn causes an increased parasitic capacitance, or vice versa. Thus, one skilled person in the art can not reduce both of the parasitic resistance and the parasitic capacitance in a conventional FinFET.
Consequently, the conventional FinFET has a delay due to a large value of the time constant RC and thus has a low switching speed.
The inventor proposed an NVM using an FinFET in U.S. Pat. No. 7,087,952, in which each FinFET has a control gate at one side of a semiconductor fin and a floating gate at the other side of the semiconductor fin. In such a floating-gate type memory device, charges tunnel from a substrate through a first gate dielectric layer to a floating gate, and are stored in the floating gate. The charges remain even in a case that the memory device is not powered. The amount of charges determines a threshold voltage (Vth) of the FinFET, due to which, a logic 1 and a logic 0 can be distinguished from each other.
The inventor proposed another NVM using an FinFET in U.S. Pat. No. 7,619,276, in which each FinFET has a floating gate at one side of a semiconductor fin, and two control gates at both sides of the semiconductor fin. The control gates have lengths larger than that of the floating gate in a direction along which the fin extends.
However, those problems in the conventional FinFET can still be found in the NVM using an FinFET. Due to the capacitive coupling between the source/drain region and the gate, NVM has a low access speed.